Application specific integrated circuits (ASICS) that require large numbers of pins for their input and output signals are more expensive to package than those with fewer pins. It is therefore of advantage if the pin numbers can be minimized.
A common interface provided on a system on chip (SOC) ASIC is a DRAM interface as many such ASICs link to a DRAM for the main memory functions.
State of the art synchronous DRAMs are usually organised internally into several banks, typically four, and have inputs for various command and address signals. To maintain the state of stored data it is necessary to refresh the memory cells within a predetermined maximum time. A typical time is 64 ms.
A 128 Mb SDRAM configured as a quad-bank typically has 134,217,728 cells (or bits), each bank having 33,554,432 bits organised as 4,096 rows by 256 columns by 32 bits. Refresh is conducted row by row, each of the 4,096 rows of each bank requiring refresh every 64 ms. This refresh may be achieved by a burst of 4,096 refresh operations to each bank every 64 ms, or more usually by performing a refresh command to a given row in each bank every 15.625 μs.
With these multi-bank SDRAM chips, refresh operation is conducted simultaneously on all banks, during which time no data operations are carried out.